SUBJECT NAME: VLSI DESIGN. SUBJECT CODE: EC UNIT I CMOS TECHNOLOGY. PART –A (2 MARKS). 1. What are four generations of Integration. EC / EC64 VLSI Design 2 Marks With Answers ECE 6th Semester Regulation | BE Electronics and Communication Engineering. Sixth Semester. 2 MARK QUESTION AND ANSWERS. ECVLSI DESIGN is CMOS technology? Complementary Metal Oxide Semiconductor (CMOS)in which.
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Performance increase comes at the cost of area.
vlso What is the importance of linear carry select Adder? Output changes 3 or more times when it changes from 1 to 0 or 0 to 1 What are the types of conditional statements? N channel transistors have greater switching speed when compared to PMOS transistors. What is the transistors CMOS technology provides? The width of the MOS transistor can be increased to reduce delay this is known as gate sizing, which will be discussed later in more details.
Regular delay control desiggn. What is known as IDDQ testing? A carry skip adder consists of a simple ripple carry adder with a special speed up carry chain called a skip chain. What is metastability and list the steps to prevent it?
EDUCATIONAL WORLD: VLSI DESIGN EC MAY/JUNE 2MARKS WITH ANSWERS
State the different types of CMOS processes. Nodes are randomly selected and faulted. What are the methods to reduce static power dissipation? No latch up 2.
It takes a sequence of precharge and conditional evaluation phases to realize the logic functions. What is dynamic power dissipation? But at the same time, latch based design is more complicated and has more issues in min timing races.
The increasing complexity of boards and the movement to technologies like multichip modules and surface-mount technologies resulted in system designers agreeing on a unified scan-based methodology for testing chips at the board.
A simulation is run with no faults inserted, and the results of this simulation are saved. Draw the basic CMOS inverter circuit.
A single layout is used repetitively for every bit in the data word. What are different generations of integration circuits? In this circuit realization the PMOS network is identical to the NMOS network rather than being the conduction complement, so the topology is called a mirror adder. Channels gate array Channel less gate array Only the interconnect is 1.
Latch based design and flop based design is that latch allows time borrowing which a tradition flip vlso does not: This provides sufficient power saving. This makes MOS dynamic circuits faster. Write the applications of transmission gate? But in the moore state machine we can calculate only next state but not output from the input and state and the output is issued according to next state.
What is fault sampling? Answerd Latch-up Due to absence of bulks transistor structures are denser than bulk silicon. What is an antifuse? Sense amplifier is needed for reading. Verilog is a general purpose hardware descriptor language. Named event control 3. An alternative would be to program the routing. Click here to sign up. The synchronizers ensure synchronization between asynchronous input and synchronous system.
This is called boundary scan. Metastability happens for the design systems violating setup or hold time requirements. Regular logic arrays b. What is the difference between latches and flip flops based designs? It is called maros skew. What is known as test data register?
What is Switch-level modeling? A type of FET in which there are no charge carriers present in the channel, when the gate voltage is in zero.
Contact cut definition 5. These tests are used after the chip is manufactured to verify that the silicon is intact.
The observability of a particular internal circuit node is the degree to which one can observe that node at the outputs of an integrated circuit. What is the fundamental goal in Device modeling? It was developed to overcome certain disadvantages of PLA, such as longer delays due to additional fusible links that result from using two programmable arrays and more circuit complexity.
The carry skip adder is shown to be superior to constant width carry skip module the advantages being greater at high precisions.